Electroforming and resistive switching in silicon dioxide resistive memory devices

Electroforming and resistive switching in SiO2 materials are investigated by controlling the annealing temperature, etching time and operating ambient. Thermal anneal in reducing ambient lowers electroforming voltage to <10 V, providing insight into possible electroformation precursors. Conductive filaments form within similar to 4 nm of sidewall surfaces in devices with an etched SiO2 layer, whereas most filaments are >10 nm from the electrode edge in devices with continuous SiO2 layers. Switching unpassivated devices fails in 1 atm air and pure O-2/N-2, with the recovery of vacuum switching at similar to 4.6 V after switching attempts in O-2/N-2 and at similar to 9.5 V after switching attempts in air. Incorporating a hermetic passivation layer enables switching in 1 atm air. Discussions of defect energetics and electrochemical reactions lead to a localized switching model describing device switching dynamics. Low-frequency noise data are consistent with charge transport through electron-trapping defects. Low-resistance-state current for <1.5 V bias is modeled by hopping conduction. A current "overshoot" phenomenon with threshold near 1.6 V is modeled as electron tunneling. Results demonstrate that SiO2-based resistive memory devices provide a good experimental platform to study SiO2 defects. The described electroforming methods and operating models may aid development of future SiO2-based resistive memory products.