Toward High Performance Quality Meeting Ic Device Manufacturing Requirements With Az Smart (Tm) Dsa Process

Significant progresses on 300 mm wafer level DSA (Directed Self-Assembly) performance stability and pattern quality were demonstrated in recent years. DSA technology is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing. We first published SMART (TM) DSA flow in 2012. In 2013, we demonstrated that SMART (TM) DSA pattern quality is comparable to that generated using traditional multiple patterning technique for pattern uniformity on a 300 mm wafer. In addition, we also demonstrated that less than 1.5 nm/3 sigma LER (line edge roughness) for 16 nm half pitch DSA line/space pattern is achievable through SMART (TM) DSA process. In this publication, we will report impacts on SMART (TM) DSA performances of key pre-pattern features and processing conditions. 300mm wafer performance process window, CD uniformity and pattern LER/LWR after etching transfer into carbon-hard mask will be discussed as well.