A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 /spl Sigma//spl Delta/ DAC

A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high frequency image of the input to be used as the output. This saves power and hardware relative to a conventional transmitter architecture by eliminating the need for mixers and intermediate frequencies. The concept is demonstrated in a 1.8 V, 0.18 /spl mu/m CMOS technology. The measured single-tone SFDR is 75 dB, SNR is 52 dB, and two-tone IMD3 is -70.8 dBc for a 17.5 MHz band centered at 942 MHz.