A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readoutHyeonjune Kim,Jiwook Kwon,Donghwan Jin,Sunil Hwang,Minchul Shin,Jongho Kang,Seungtak Ryucustom integrated circuits conference(2014)引用 25|浏览37暂无评分AI 理解论文溯源树样例生成溯源树,研究论文发展脉络Chat Paper正在生成论文摘要