A Low-Power 22-Bit Incremental Adc With 4 Ppm Inl, 2 Ppm Gain Error And 2 Mu V Dc Offset

A lowpower 22bit incremental ADC, including an on-chip digital filter and a lownoise/lowdrift oscillator, w as realized in a 0.6-mu m CMOS process. It incorporates a novel offseteancellation scheme based on fractal sequences, a novel highaccuracy gain control circuit, and a novel reducedcomplexity realization for the onchip sine filter. The measured output noise was 0.28 ppm (2.8 mu V(RMS)), the dc offset 2 mu V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7 - 5 V supply, and draws only 125 mu A current during conversion.