22nm technology yield optimization using multivariate 3D virtual fabrication

B Cipriany,Basanth Jagannathan,G Costrini,A Noemaun, Keiji Onishi, Srinivasa Rao Pemmaraju Venkata Lakshmi Narasimha,Bo Zhang,C D Sheraw, Jason Meiring,M Kumar,K Nummy,Ning Zhan, H Nanjundappa,J Norum,Stephen S Furkay,Rayaz Ahmed Malik,P Agnello,David M Fried,Kenneth B Greiner,Daniel Faken, S Breit

Simulation of Semiconductor Processes and Devices（2013）

引用 5|浏览66

暂无评分

摘要

We present a technology development methodology that relies on 3D virtual fabrication to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ramp of high-performance 22nm SOI CMOS technology. Based on virtual metrology, dedicated testsite structures were designed and implemented, with electrical results corroborating virtual findings, validating the methodology. This 3D virtual fabrication technique was used to implement a delicate process change, and the same testsite structures validated the improved process window yield.

查看译文

关键词

cmos integrated circuits,integrated circuit measurement,integrated circuit testing,integrated circuit yield,silicon-on-insulator,soi cmos technology,multilevel process variation,multivariate 3d virtual fabrication,process window yield,size 22 nm,technology yield optimization,test site structures,virtual metrology,yield ramp,22nm,cmos,modeling,n-p transition,testsite,virtual fabrication,yield optimization,silicon on insulator

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要