An energy-efficient switching technique for 2-bit/cycle SAR ADCs
ISMICT（2015）
摘要
A new energy-efficient switching technique for 2bit /cycle successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed switching technique achieves 97.91% less switching energy and 75% less total capacitance over the conventional architecture. A LSB correction method is also proposed to relax the accuracy requirement on the comparator. The prototype was designed in a TSMC 90-nm CMOS process technology. The post-layout simulation results show that the ADC achieves a SNDR of 59.83 dB, power consumption of 0.879 mW and FoM of 10.94 fJ /conversion-step at 100 MHz sampling rate with a 1 V supply voltage.
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关键词
cmos integrated circuits,analogue-digital conversion,capacitance,circuit simulation,integrated circuit layout,low-power electronics,2-bit /cycle sar adcs,cmos process technology,analog-to-digital converters,energy-efficient switching technique,frequency 100 mhz,least-significant-bit correction technique,post-layout simulation,power 0.879 mw,power consumption,size 90 nm,successive approximation register,switching energy,voltage 1 v,merged capacitor switching,successive approximation analog-to-digital converter,wireless sensor node,energy efficiency,communications technology,switches,accuracy,capacitors,low power electronics
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