Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Yih Wang,Umut Arslan,Nabhendra Bisnik,Ruth Brain,Swaroop Ghosh,Fatih Hamzaoglu,Nick Lindert,Mesut Meterelliyoz,Joodong Park,Shigeki Tomishima,Kevin Zhang

Electron Devices Meeting（2013）

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摘要

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

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关键词

cmos integrated circuits,dram chips,low-power electronics,optimisation,system-on-chip,gbit edram,critical circuits,design cooptimization,edram bitcell,high performance edram technology,high-performance trigate cmos soc technology,low-power 22nm trigate cmos soc technology,noise reduction circuit techniques,retention time optimization,size 22 nm,temperature 95 c,system on chip,low power electronics

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