A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

Shaohua Wan,Chehsun Kuo,Soonjyh Chang,Guanying Huang,Chunpo Huang,Goh Jih Ren, Kaitzeng Chiou,Chenghsun Ho

Solid-State Circuits Conference（2013）

引用 23|浏览9

暂无评分

摘要

A high speed successive approximation (SAR) ADC requires reference voltage buffers with high driving capability. Moreover, the power consumption of the reference buffers is usually several times larger than that of the SAR ADC itself. Three techniques are adopted to mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. A 10b 50MS/s ADC based on the proposed techniques is presented. The prototype ADC was fabricated in 40nm LP 1P7M CMOS technology. It consumes 0.47 mW at 50 MS/s from 1.1V supply voltage and achieves ENOB of 9.18-bit and figure of merit (FoM) of 16 fJ/conversion-step. The active area is 0.0114 mm2.

查看译文

关键词

cmos integrated circuits,analogue-digital conversion,buffer circuits,driver circuits,logic design,reference circuits,cmos technology,sar adc,driving capability,high speed successive approximation,power 0.47 mw,power consumption,reference voltage buffers,size 40 nm,voltage 1.1 v

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要