A 32-Gbps 4×4 passive cross-point switch in 45-nm SOI CMOS

Radio Frequency Integrated Circuits Symposium（2013）

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摘要

This paper presents a passive 4x4 cross-point switch in 45-nm SOI CMOS technology for LVDS systems with near-zero power consumption. The CMOS switch dimensions and layout structures are optimized using fullwave electromagnetic simulations for the highest 3-dB bandwidth in order to maximize the data-rate for digital signal transmission. Also, a novel series switch is used between the cells to enhance the bandwidth. The 4×4 switch matrix results in a measured 3-dB bandwidth of ~ 20 - 25 GHz (depending on the path) and an isolation > 40 dB at 26.5 GHz. The group delay variation is <; ±5 psec, and results in very low jitter as seen from eye measurements (<; 1.3 psec). Good eye-openings are obtained at 26 Gbps and up to 31.5 Gbps. The design is readily scalable to an 8×8 cross-point switch matrix.

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关键词

cmos integrated circuits,delays,jitter,matrix algebra,power consumption,silicon-on-insulator,cmos switch dimension,lvds system,soi cmos,bandwidth 20 ghz to 25 ghz,bit rate 26 gbit/s to 31.5 gbit/s,bit rate 32 gbit/s,cross-point switch matrix,digital signal transmission,eye measurement,frequency 26.5 ghz,full-wave electromagnetic simulation,gain 3 db,group delay variation,layout structure,near-zero power consumption,passive cross-point switch,size 45 nm,silicon on insulator,optical switches,bandwidth

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