A 60 GHz multi-Gb/s system demonstrator utilizing analog synchronization and 1-bit data conversion

Ahmet Cagri Ulusoy,Stefan Krone,Gang Liu,Andreas Trasser,Falko Guderian,Bjoern Almeroth,Atheer Barghouthi,Marcus Hellfeld,Stefan Schumann,Corrado Carta,Carlos Estan,Kai Dombrowski,Veselin Brankovic,Dusan Radovic,Frank Ellinger,Gerhard Fettweis,H W Schumacher

Silicon Monolithic Integrated Circuits in RF Systems（2013）

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摘要

In this paper, a 60 GHz system demonstrator for multi-Gb/s, short-range, line-of-sight communications is presented. The system utilizes a highly efficient receiver architecture with phase noise suppression capability, which performs carrier synchronization in the analog domain, eliminating the need for high speed, high precision analog-to-digital converters. In the presented demonstrator, with only 1-bit data conversion at the transmitter and receiver, an error-free maximum raw data rate of 3.45 Gb/s is achieved using BPSK modulation over a wireless transmission distance of up to 1m. A more sophisticated modulation capability is demonstrated as well for a raw data rate of 6.9 Gb/s and a bit error rate of 10-5 usina QPSK modulation.

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关键词

analogue-digital conversion,millimetre wave circuits,millimetre wave receivers,modulators,phase noise,quadrature phase shift keying,radio receivers,radio transmitters,synchronisation,bpsk modulation,qpsk modulation,analog carrier synchronization,analog-to-digital converter,bit rate 3.45 gbit/s,bit rate 6.9 gbit/s,data conversion,error-free maximum raw data rate,frequency 60 ghz,multigb/s short-range line-of-sight communication system demonstrator,phase noise suppression capability,receiver architecture,transmitter,wireless transmission distance,word length 1 bit,analog to digital converters,mmics,integrated circuit packaging,ultra wideband communication,wireless communication

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