Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length
VLSI Technology（2012）
摘要
We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching ION,n/ION,p=1148/1014μA/μm drive current at IOFF,n/IOFF,p=55/16nA/μm leakage current (VDD=1V) with excellent VT-matching (AVT <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves ION,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.
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关键词
cmos integrated circuits,ge-si alloys,mosfet,semiconductor device manufacture,silicon-on-insulator,cmos,sige,contact-etch-stop-layers,drive current,fully depleted silicon-on-insulator,leakage current,mechanical stressors efficiency,planar fdsoi nmosfet,planar fdsoi pmosfet,size 14 nm,logic gates,silicon,silicon on insulator,stress
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