The future of CMOS scaling - parasitics engineering and device footprint scaling
Beijing（2008）
摘要
We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level.
更多查看译文
关键词
cmos integrated circuits,field effect transistors,cmos scaling,contacted gate pitch,device footprint scaling,one-dimensional fet,parasitic capacitance,parasitics engineering
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要