Foreground Detection Optimization for SoCs embedded on Smart Cameras

In this paper we study the effectiveness of a set of optimizations applied on a foreground detection and background maintainance algorithm. The optimizations were specifically devised to run in real time on hardware architectures embedded on commercial smart cameras. In order to achieve these aims we focused our attention on two kinds of optimizations based on the elimination of floating-point operations and the adoption of SIMD instructions. The optimized version of the algorithm has been tested on two RISC architectures (CRISv32 and MIPS 32Kc) considering different stream resolutions. The results confirm the effectiveness of the proposed solutions, which allows to process in real-time up to VGA resolution.