A 1-V, 1.2-mA fully integrated SoC for digital hearing aids.

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130nm CMOS technology. The measurement results show that the analog front-end has up to 88dB signal-to-noise ratio. And the DSP platform consumes about 0.86mA current at 8MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2mA at 1V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.