An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Applications

A stacked 2.4-GHz CMOS power amplifier (PA) with a mode switching scheme is proposed to enhance the back-off efficiency for wireless local area network applications. By means of dynamically tuning the bias and optimal load with a power-detecting controller, the proposed mode switching scheme effectively improves the power-added efficiency (PAE) of the PA by ×2 at 5-dB back-off power. Besides, with the transistor stacking and envelope-tracked self-biasing techniques, the PA, powered by a 5.6-V supply, achieves an output P1dB of 27 dBm with a PAE of 26.1% and an output P1dB of 22 dBm with a PAE of 21.8% in high-power mode and low-power mode, respectively, while occupying only a 1.5- mm2 die area in 180-nm CMOS. In the closed-loop power-detecting mode, the PA achieves an adjacent channel leakage ratio of -22.6 dBc and an error vector magnitude of -26.9 dB at 23-dBm output power for 120-Mb/s 7.6-dB peak-to-average power-ratio 64 quadrature amplitude modulation 802.11n signals.