Dual floating gate flash cell using single poly processes

A novel memory device with dual floating-gate is investigated in this paper. The fabrication process of this device is compatible with the standard logic CMOS process flow using single gate poly. It can store 2 bits in a single cell without increasing the cell size. This study provides the fabrication process flow of the dual floating-gate devices. The transfer characteristics, programming, reading, and erasing performances are investigated. The crosstalk between these two floating-gates is also studied. Simulation results show a prosperous prospect of this device. It is promising for high density embedded FLASH applications.