A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS.

ISSCC(2011)

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摘要
The current trend in high-performance audio DACs is to use fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch. In addition to the element mismatch, dynamic error sources such as asymmetrical switching, clock skew, and parasitic memory are major hindrances to achieve distortion and dynamic range targets. The resulting dependence of present symbol error to the past symbol is referred to as inter-symbol-interference (ISI), and is a function of the switching activity of all the individual DAC elements. Unfortunately, the popular mismatch-shaping algorithms (e.g., rotation-DWA) are addressing only the static mismatch problem. They typically increase the switching activity thus amplify ISI errors. Furthermore, the error comes often in the form of spurious tones with signal-dependent frequency (FM modulation [3]) that ruins the low-amplitude performance (harmonics for a −60dB signal) which is critical for the perceived sound quality. A common remedy is to add a digital DC offset to shift the tones out of band. However, this merely moves the problematic amplitude region, and does not solve the problem. Moreover, ISI errors often limit the large signal THD as a result of a strong signal-dependent modulation of the element transition rate.
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关键词
noise,pll,integrated circuit design,eda tools,intersymbol interference,frequency modulation,sensitivity,cmos integrated circuits,switches,cmos
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