Analysis And Mitigation Of Phase Noise And Sampling Jitter In Ofdm Radio Receivers

This article addresses the analysis and digital signal processing (DSP)-based mitigation of phase noise and sampling clock jitter in orthogonal frequency division multiplexing (OFDM) radios. In the phase noise studies, the basic direct-conversion receiver architecture case is assumed with noisy downconverting oscillator. In the sampling jitter case, on the other hand, the so-called direct-radio-frequency-sampling receiver architecture is deployed utilizing bandpass sub-sampling principle. The basis for the DSP-based impairment mitigation techniques is first formed using analytical receiver modeling with incoming OFDM waveform, where the effects of both oscillator phase noise and sampling clock jitter are mapped to certain type subcarrier cross-talk and distortion compared to ideal receiver case. Then iterative detection principles and interpolation techniques are developed to essentially estimate and cancel the subcarrier distortion. Also some related practical aspects, like channel estimation, are addressed. The performance of the proposed mitigation techniques is analyzed and verified with extensive computer simulations. In the simulations, realistic phase-locked-loop-based oscillator models are used for phase noise and sampling clock jitter. In addition, different received signal conditions like plain additive white Gaussian noise channel and extended ITU-R Vehicular A multipath channel are considered for practical purposes. Altogether the obtained results indicate that the effects of oscillator and sampling clock instabilities can be efficiently reduced using the developed signal processing techniques.