Exploring emerging three-dimensional integration and memory technologies in processor microarchitecture design

Aggressive scaling of process technologies has allowed the semiconductor industry to keep pace with Moore’s Law for the past several decades. However, CMOS process technology is approaching its limits and interconnects are becoming a major performance bottleneck. Moreover, microprocessor designers are facing an increasing number of related challenges, including high power consumption, low reliability, enlarged performance gap between high-speed processor and off-chip memory, and increased demand for high-density memory. In response to these issues, new devices and manufacturing process technologies have been proposed. Among them, three-dimensional (3D) integration is a promising technology for extending Moore’s Law by stacking multiple layers of processed silicon with very high-density, low-latency, and vertical interconnects. Phase Change Memory (PCM) is another emerging technology, which is regarded as a promising candidate for the next generation of computer memory and may help solve the power and reliability challenges faced by designers. However, these emerging technologies pose unanswered questions to the field of computer architecture: What are the impacts of these emerging technologies on the microarchitecture design? How can these resources be leveraged effectively to design future processor innovatively? What new challenges are introduced and how can they is addressed? To attack these questions, this research adopts a multi-layer holistic approach, including investigating the characteristics of emerging technologies from a microarchitecture perspective at the device and circuit level; proposing innovative architectures that explore the benefits and mitigate design issues at the microarchitecture level; and designing OS schemes at the system level for better interaction between OS and microarchitecture. The first task in this work is a study of the reliability benefits of 3D integration. The study reveals opportunities for leveraging the structure of vertical stacking and the heterogeneous process technologies to achieve enhanced reliability. Next, a memory architecture built from PCM is proposed to achieve scalable, reliable, high performance, low power, and thermal friendly features for both conventional 2D microprocessor system and die-stacked microarchitecture in the upcoming 3D-stacking era. To effectively integrate PCM into a conventional memory hierarchy, microarchitecture- and system-level techniques are proposed to combat several issues of PCM-based memory, including long write latency, large programming power consumption, high susceptibility to process variation, and low reliability. Further, the application of new memory technologies on cache architecture is investigated. Versatile cache architecture is proposed that employs non-volatile SRAM cell design, which integrates new memory devices into conventional SRAM cells. This new design opens new opportunities to improve the efficiency of cache management as well as enabling versatile and enriched functionalities for cache architecture.