SimPL: An effective placement algorithm

IEEE Trans. on CAD of Integrated Circuits and Systems(2012)

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摘要
We propose a self-contained, flat, quadratic global placer that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel look-ahead legalization algorithm. Our placer SimPL outperforms mPL6, FastPlace3, NTUPlace3, APlace2, and Capo simultaneously in runtime and solution quality, running 7.10 times faster than mPL6 (when using a single thread) and reducing wirelength by 3% on the ISPD 2005 benchmark suite. More significant improvements are achieved on larger benchmarks. The new algorithm is amenable to parallelism, and we report empirical studies with SSE2 instructions and up to eight parallel threads.
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关键词
timing-closure flows,algorithms,ispd 2005 benchmark suite,simpl,aplace2,lower-bound placement,placer simpl,novel rough legalization algorithm,global placement,final solution,upper-bound placement,look-ahead legalization algorithm,effective placement algorithm,physical design,mpl6,self-contained flat quadratic global placer,circuit layout cad,solution quality,multiprocessing systems,placement,computational complexity,force-directed algorithm,ntuplace3,optimization,fastplace3,multicore,rough legalization algorithm,placement algorithm,integrated circuit layout,layout,timing-closure flow,benchmark suite,capo,mathematical model,linear systems,convergence,clustering algorithms,lower bound,upper bound,finite state machine
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