Dependence of Analog and Digital Performances on Mechanical Film Stress of ILD Layers in Nanoscale CMOSFETs

In this study, film-stress-induced device performance variation is characterized in terms of digital and analog performances. Interlayer dielectric (ILD) layers such as PECVD Si3N4 and LPCVD SiON with different stress-affected saturation currents and off-state leakage Currents are investigated extensively. To further analyze stress effects, the film stress of PECVD Si3N4 is varied front compressive stress to tensile stress. It is shown that tensile stress improved NMOS performance through the decrease of interface state density (D-it) and the increase of carrier mobility. In the case of PMOS with highly tensile stress, the mobility is decreased due to the increase of D-it. The oxide fixed charge Q(f) of PMOS is also reduced evidently by the tensile stress film.