Integrated CPU and L2 cache Frequency/Voltage Scaling using Supervised Learning

Multiple clock domain (MCD) chip design addresses the problem of the increasing clock skew in the different chip units. MCD design opens the op- portunity for independentpower managementin each domain when used in con- junction with dynamic voltage scaling (DVS). A significant power and energy improvement has been shown for finercontrol of each domain voltage rather than managing the chips single voltage, as in traditional chips with global DVS. How- ever,publishedpolicies in the literature focus on eachdomain in isolation without considering the possible inter-domain effects when varying their clock/voltage from other domain. In this paper we propose to use a supervised machine learning technique to au- tomatically derive an integrated CPU-core and on-chip L2-cache DVS policy. Our policy relies on simple performance counters that can be easily monitored. We discuss the machine learning process and the implementation issues associ- ated with our technique.We show that our derived policy improves on traditional power management techniques used in MCD chips. Our technique saves up to 34% (10% on average) over a DVS techniques that apply independent DVS de- cisions in each domain. Moreover, energy and energy-delay product results are within 3% of a near-optimal scheme.