100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications
CICC（2010）
摘要
This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3~10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18μm CMOS process and operates from 100MHz to 1GHz.
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关键词
cmos process,mobile application,frequency range selector,time-to-digital converter,open loop addll,tdc,fast lock-time,size 0.18 mum,fast-lock,wide-range,frequency convertors,open loop architecture,fast-lock wide-range all-digital delay locked loops,frequency 100 mhz to 1 ghz,multipath delay line,delay lock loops,open-loop dll,mobile communication,delay lock loop,calibration,synchronization,time to digital converter,high resolution
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