Refinement of Unified Random Access Memory

Seong-Wan Ryu,Jin-Woo Han,Chung-Jin Kim,Sung-Jin Choi,Sungho Kim,Jin-Soo Kim,Kwang Hee Kim,Jae-Sub Oh,Meyong-Ho Song,Gi-Sung Lee,Yun Chang Park,Jeoung Woo Kim,Yang-Kyu Choi

Electron Devices, IEEE Transactions（2009）

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摘要

This paper investigates how gate height (Hg), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower Hg yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower Hg shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.

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关键词

partially depleted silicon-on-insulator region,one-transistor dram,gate height,partially depleted silicon-on-insulator (pdsoi),nonvolatile memory,dram chips,one-transistor dram (1t-dram),retention characteristics,silicon-on-insulator,sonos,finfet sonos device,impact ionisation,impact ionization,mosfet,charge storage,finfet,unified random access memory,unified random access memory (uram),scalability,sensors,controllability,logic gates,silicon on insulator,system on a chip,helium

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