Smv Methodology Enhancements For High Speed I/O Links Of Socs

Andres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez,Israel Diaz-Castro, Brenda Marcial,Gaston Motola-Acuna,Edgar-Andrei Vega-Ochoa

VLSI Test Symposium（2014）

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摘要

This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.

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关键词

System-on-Chip,Post-Silicon Electrical Validation,System Marginality Validation,High Speed I/O,Unit per Million

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