Making secure processors OS- and performance-friendly

TACO(2009)

引用 21|浏览28
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摘要
In today's digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors that utilize hardware-based memory encryption and integrity verification to protect the privacy and integrity of computation even from sophisticated physical attacks. However, currently proposed schemes remain hampered by problems that make them impractical for use in today's computer systems: lack of virtual memory and Inter-Process Communication support as well as excessive storage and performance overheads. In this article, we propose (1) address independent seed encryption (AISE), a counter-mode-based memory encryption scheme using a novel seed composition, and (2) bonsai Merkle trees (BMT), a novel Merkle tree-based memory integrity verification technique, to eliminate these system and performance issues associated with prior counter-mode memory encryption and Merkle tree integrity verification schemes. We present both a qualitative discussion and a quantitative analysis to illustrate the advantages of our techniques over previously proposed approaches in terms of complexity, feasibility, performance, and storage. Our results show that AISE+BMT reduces the overhead of prior memory encryption and integrity verification schemes from 12% to 2% on average for single-threaded benchmarks on uniprocessor systems, and from 15% to 4% for coscheduled benchmarks on multicore systems while eliminating critical system-level problems.
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关键词
memory encryption,merkle tree integrity verification,independent seed encryption,memory integrity verification,additional key words and phrases: secure processor architectures,virtual memory,tree-based memory integrity verification,virtualization,secure processor,prior memory encryption,prior counter-mode memory encryption,integrity verification,counter-mode-based memory encryption scheme,integrity verification scheme,hardware-based memory encryption,quantitative analysis,inter process communication,computer security,processor architecture
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