Design And Implementation Of Hybrid Multicore Simulators

Hybrid multicore architecture consisting of tightly-integrated very long instruction word (VLIW) and superscalar processors can potentially take advantage of the heterogeneity of different cores to attain better performance. However, to implement or simulate a hybrid multicore processor is a challenging task due to the interactions of tightly integrated cores with different architectures/microarchitectures. In this paper, we design and implement two hybrid multicore architecture simulators for multi-program and multicore (MPMC) paradigm and single-program and multicore (SPMC) respectively. Based on these simulators, we provide preliminary results to evaluate the performance of the hybrid multicore processor for both multi-threaded and single-threaded programs.