A hierarchical implementation of Hadamard transform using RVC-CAL dataflow programming and dynamic partial reconfiguration.
DASIP（2012）
关键词
Hadamard transforms,data flow computing,field programmable gate arrays,hardware description languages,parallel languages,power consumption,specification languages,video coding,DPR design flow,DPR technique,FPGA area,Hadamard blocks,Hadamard transform module,MPEG-RVC video standard,RVC-CAL dataflow approach,RVC-CAL dataflow programming,RVC-CAL description,RVC-CAL language,RVC-CAL tool,Virtex-5 FPGA board,dataflow models,design process,dynamic partial reconfiguration technique,execution time,hardware description,hierarchical architecture,hierarchical implementation,interconnected blocks,power consumption,xilinx tools,Dynamic partial reconfiguration,FPGA,Hadamard transform,RVC-CAL,design approach,execution time,hierarchical architecture
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