The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor.

Dieter F. Wendel,Ronald N. Kalla,Robert Cargnoni,Joachim G. Clabes,Joshua Friedrich, R. Frech,James A. Kahle,Balaram Sinharoy,William J. Starke, Scott Taylor,Steve Weitzel,Sam G. Chu,Md. Saiful Islam,Victor V. Zyuban

ISSCC（2010）

引用 111|浏览76

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摘要

POWER7TM the next generation processor of the POWERTM family is introduced. The 8-core chip, supporting 32 threads, is implemented in 45 nm 11 M CMOS SOI. The 32 kB L1 caches feature 1 read port banked write for the l-cache and 2 read ports banked write for the Dcache. The on-chip cache hierarchy consists of a 256 kB fast, private SRAM L2 and a 32MB shared L3, implemented in embedded DRAM.

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关键词

DRAM chips,SRAM chips,cache storage,microprocessor chips,multiprocessing systems,parallel architectures,8-core chip,CMOS SOI,DRAM,Dcache,POWER7,memory size 256 KByte,memory size 32 KByte,memory size 32 MByte,on-chip cache hierarchy,parallel server processor,private SRAM L2,read port banked write,scalable multicore high end server processor,shared L3,size 45 nm

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