Conservative row activation to improve memory power efficiency.

ABSTRACTWith the fast improvement on memory bandwidth and capacity, the memory power consumption has become a major contributor to the overall system power profile. Due to the increasing importance of memory-level parallelism at the multi-core era, most memory scheduling schemes eagerly exploit such parallelism to optimize performance. A common policy used by memory controllers today is, whenever possible, always trying to open memory banks for pending requests to maximize bank-level parallelism and throughput. However, we find that this is neither power optimal nor necessary for maintaining performance because usually many banks are open while waiting for the data bus ownership. To address this issue, we propose a "Conservative Row Activation" scheme that delays the row activation operation of a request to an idle rank until its corresponding column access will not be blocked by the busy data bus. This can reduce the memory power with negligible performance impact by allowing a rank to stay at the low-power mode longer. To minimize performance impact, our scheme monitors the data bus transactions and reserves bus slots for column commands at the earliest possible time. The detailed simulation results indicate that our scheme can reduce the memory power consumption of a group of quad-core multi-programming memory-intensive workloads with SPEC2006 applications by 5.6% on average. It may even improve the performance slightly (by 0.3% on average), because the data bus utilization can be improved by giving column accesses higher priority than other commands.