Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL

Ivan Blunno,Luciano Lavagno

ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems（2000）

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摘要

Delay-Insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations ...

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关键词

Delay-Insensitive specifications model,communication channel,varying delay,Automated Synthesis,Behavioral Verilog HDL

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