Timing verification on a 1.2M-device full-custom CMOS design

Static timing verification on a large full-custom design is an extremely challenging problem for which no complete solution exists. In this paper, we present our experience on the timing verification of our next generation CMOS CPU design using an internally developed tool, NTV. The entire chip, which consists of 1.2M transistors and 500K nodes, has been verified by NTV in less than 7 CPU hours on a VAX-8800. 42K timing constraints were verified and 350K signal paths were traced. Among the reported critical paths, 85% were already known to designers and the remaining 15’%0were unforeseen critical paths.