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Surendra Hemaram (Student Member, IEEE) received the M. Tech degree in the Department of Electrical Engineering at Indian Institute of Technology Jodhpur, Rajasthan, India in 2021. He received his B.E. degree in Instrumentation Engineering from University of Mumbai, Mumbai, India in 2016. His areas of interest include signal integrity, power integrity, metaheuristic optimization, and soft computing techniques for designing circuits and systems, spintronic computing, and variability analysis. He has authored or coauthored several research papers related to power integrity, metaheuristic optimization for circuits and systems, and variability analysis of CMOS circuits and systems.
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论文共 8 篇作者统计合作学者相似作者
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2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)pp.752-757, (2024)
2023 IEEE 41st VLSI Test Symposium (VTS)pp.1-7, (2023)
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2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)pp.1-6, (2022)
2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)pp.1-4, (2021)
2020 IEEE MTT-S Latin America Microwave Conference (LAMC 2020)pp.1-3, (2021)
2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposiumpp.554-558, (2021)
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