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VLSI, asynchronous circuit design and architecture, timing analysis, and formal verification.
Digital CMOS VLSI provides a fantastic template for creating and engineering communication and control circuitry. Research focuses on architecture, circuit styles, and CAD. The Pentium front end is an example.
Many second order effects are becoming significant in multi-GHz circuits. A primary DSM effect studied is the variation created through multiple input switching (MIS), and how to generate and prune the worst case vectors. Research is also focused on evaluating and mitigating the effects of process variation.
Function and timing in circuits are highly interrelated. Verifying the timed behavior using timing variables has been relatively unsuccessful due to computational complexity. The novel Relative Timing research moves timing into the logic domain through relative logic relationships on the ordering of signal transitions. These techniques show order-of-magnitude improvement using SAT methods over the previous best approaches.
Digital CMOS VLSI provides a fantastic template for creating and engineering communication and control circuitry. Research focuses on architecture, circuit styles, and CAD. The Pentium front end is an example.
Many second order effects are becoming significant in multi-GHz circuits. A primary DSM effect studied is the variation created through multiple input switching (MIS), and how to generate and prune the worst case vectors. Research is also focused on evaluating and mitigating the effects of process variation.
Function and timing in circuits are highly interrelated. Verifying the timed behavior using timing variables has been relatively unsuccessful due to computational complexity. The novel Relative Timing research moves timing into the logic domain through relative logic relationships on the ordering of signal transitions. These techniques show order-of-magnitude improvement using SAT methods over the previous best approaches.
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2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)pp.60-70, (2023)
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2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)pp.71-77, (2023)
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Guillermo H. Makar,Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro,Kenneth S. Stevens,Roberto Suaya
PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)pp.794-799, (2017)
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