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Jay Im received the B.S. degree in electronics engineering and the M.S. degree in physics from Seoul National University, Seoul, South Korea, and the Ph.D. degree in physics from the Ohio State University, Columbus, OH, USA, in 2001. His dissertation topic was nanometer-scale study of metal contacts to wide-bandgap semiconductor materials, including SiO, SiC, and GaN.
He was with Silicon Storage Technology, Inc., Sunnyvale, CA, USA, from 2001 to 2004 as a Process/Device Engineer, where he was involved in developing CMOS compatible flash memory IP. He joined Xilinx Inc., San Jose, CA, USA, in 2004, where he has been involved in embedded non-volatile memory technology development, E-fuse PDK development, custom design of OTP macro in field-programmable gate array (FPGA), RTL design of interface block for foundry IP, and led the pre-production diagnostic module group. He has been leading a Design Team, developing analog front end for high-speed SERDES PHY to be embedded in FPGA, and is in charge of the SERDES IP development for the next generation FPGA.
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