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Anup P. Jose (S'01–M'06) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, India, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from Columbia University, New York, NY, in 2003 and 2006, respectively. His research focused on low-latency low-power interconnects for on-chip networks.
He was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, for the summers of 2002–2004 where he worked on on-chip jitter measurement circuits and an on-chip spectrum analyzer. During the summer of 2005, he was with the IBM Austin Research Laboratory, Austin, TX, where he was responsible for the design of on-chip sampling circuits in 65-nm technology. He is currently working as a Senior Design Engineer with the high-speed I/O group at AMD's Boston Design Center.
Mr. Jose received the 2005 Best Paper Award at the European Solid-State Circuits Conference.
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VLSI Technology and Circuitspp.1-2, (2023)
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Dongwon Park, Jongman Bae, Hyunsu Kim,Amir Amirkhany,Anup Jose, Frank Seto,Dale Stolitzka, Kyungyoul Min, Wonjun Choe
SID Symposium Digest of Technical Papersno. 1 (2022): 159-162
SID Symposium Digest of Technical Papersno. 1 (2019): 334-337
semanticscholar(2016)
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